The present invention relates in general to the field of mass storage devices, and more particularly to a system and method of providing error margin information for threshold errors and peak shift errors, respectively, in read channel circuits.
Hard disk drives such as the exemplary drive 10 illustrated in FIG. 1 include a stack of magnetically coated platters 12 that are used for storing information. The magnetically coated platters 12 are mounted together in a stacked position through a spindle 14 which may be referred to as a platter stack. The platter stack is typically rotated by a motor that is referred to as a spindle motor or a servo motor (not shown). A space is provided between each platter to allow an arm 18 having a read/write head or slider 20 associated therewith to be positioned on each side of each platter 12 so that information may be stored and retrieved. Information is stored on each side of each platter 12 and is generally organized into sectors, tracks, zones, and cylinders.
Each of the read/write heads or sliders 20 are mounted to one end of the dedicated suspension arm 18 so that each of the read/write heads may be positioned as desired. The opposite end of each of the suspension arms 18 are coupled together at a voice coil motor 16 (VCM) to form one unit or assembly (often referred to as a head stack assembly) that is positionable by the voice coil motor. Each of the suspension arms 18 are provided in a fixed position relative to each other. The voice coil motor 16 positions all the suspension arms 18 so that the active read/write head 20 is properly positioned for reading or writing information. The read/write heads 20 may move from at least an inner diameter to an outer diameter of each platter 12 where data is stored. This distance may be referred to as a data stroke.
Hard disk drives also include a variety of electronic circuitry for processing data and for controlling its overall operation. This electronic circuitry may include a preamplifier, a read channel, a write channel, a servo controller, a motor control circuit, a read-only memory (ROM), a random-access memory (RAM), and a variety of disk control circuitry (not shown) to control the operation of the hard disk drive and to properly interface the hard disk drive to a system bus. The preamplifier may contain a read preamplifier and a write preamplifier that is also referred to as a write driver. The preamplifier may be implemented in a single integrated circuit or in separate integrated circuits such as a read preamplifier and a write preamplifier or write driver. The disk control circuitry generally includes a separate microprocessor for executing instructions stored in memory to control the operation and interface of the hard disk drive.
Hard disk drives perform write, read, and servo operations when storing and retrieving data. Generally, a write operation includes receiving data from a system bus and storing the data in the RAM. The microprocessor schedules a series of events to allow the information to be transferred from the RAM to the platters 12 through the write channel. Before the information is transferred, the read/write heads 20 are positioned on the appropriate track and the appropriate sector of the track is located. The data from the RAM is then communicated to the write channel as a digital write signal. The write channel processes the digital write signal and generates an analog write signal. In doing this, the write channel may encode the data so that the data can be more reliably retrieved later. The digital write signal may then be provided to an appropriate read/write head 20 after first being conditioned by the preamplifier. Writing data to the recording medium or platter 12 is typically performed by applying a current to a coil of the head 20 so that a magnetic field is induced in an adjacent magnetically permeable core, with the core transmitting a magnetic signal across a spacing of the disk to magnetize a small pattern or digital bit of the media associated with the disk.
Circuitry associated with a read operation is illustrated in FIG. 2, and designated at reference numeral 30. In a read operation, the appropriate sector to be read is located and data that has been previously written to the platters 12 is detected. The appropriate read/write head 20 (illustrated as a magneto-resistive load 20a in FIG. 2) senses the changes in the magnetic flux and generates a corresponding analog read signal. The analog read signal is provided back to the electronic circuitry where a preamplifier circuit 32 amplifies the analog read signal. The amplified analog read signal is then provided to a read channel circuit 34 where the read channel conditions the signal and detects xe2x80x9czerosxe2x80x9d and xe2x80x9conesxe2x80x9d from the signal to generate a digital read signal. The read channel may condition the signal by amplifying the signal to an appropriate level using, for example, automatic gain control (AGC) techniques. The read channel may then filter the signal to eliminate unwanted high frequency noise, equalize the channel, perform the data recovery from the signal, and format the digital read signal. The digital read signal is then transferred from the read channel and is stored in the RAM (not shown). The microprocessor may then communicate to the host that data is ready to be transferred.
Each bit of information stored on a disk or platter 12 corresponds to a magnetic transition, and a read head generates electrical signals corresponding to the magnetic transition. A xe2x80x9c1xe2x80x9d may be used to designated the presence of a magnetic transition, and a xe2x80x9c0xe2x80x9d to designate the lack of a magnetic transition. The read head generates either a positive or a negative pulse for each magnetic transition depending on the polarity of the transition. Data are read from the disk by processing the pulse transition responses.
The read channel circuit 34 may be implemented using any of a variety of known or available read channels. For example, the read channel 34 may be implemented as an analog peak detection type read channel or as a digital peak detection type of read channel. One conventional analog peak detection method is to differentiate the signal and detect zero crossings of the signal derivative. The signal derivative is zero for local minimums and local maximums. The amplitude of the signal where the derivative is zero is then compared to a threshold level to identify peak samples. Such peak detection methods typically have a sample comparison window two to three samples wide.
A conventional digital peak detection method includes converting the analog samples to digital samples, and then comparing a sample to the previous sample and the subsequent sample. If the sample is greater than the previous and subsequent samples, then the sample is compared with a threshold level. If the sample exceeds the threshold then the sample is identified as a pulse or peak. Similar to the conventional analog peak detection system, such digital methods typically have a peak comparison window that is three samples wide.
Two primary sources of reading error in digital peak detection read channels are threshold errors and peak shift errors. In one type of threshold error, an error occurs when the peak of the pulse falls below the threshold and is not detected. This source of threshold error is often called a xe2x80x9cmissing bitxe2x80x9d error. Another type of threshold error occurs when a peak is falsely identified. This type of threshold error is often referred to an xe2x80x9cextra bitxe2x80x9d error. A peak shift error is often called a xe2x80x9cbit shift errorxe2x80x9d because the peak (associated with a data bit) is shifted undesirably into the next timing window.
There is a need in the art to provide read channel circuits having improved reliability and therefore there is a need for systems and methods for characterizing such circuit reliability with respect to threshold errors and peak shift errors, respectively.
The present invention relates to a system and method of providing a channel quality monitor for digital peak detection systems in read channels which will provide a user an indication of how close the read channel is to experiencing threshold type errors and peak shift type errors, respectively. Such an indication thus provides the user with information relating to the reliability of the read channel design.
The present invention relates to a system and method of characterizing the reliability of a read channel circuit with respect to threshold type errors. The invention identifies a peak sample data point and identifies a threshold margin associated therewith, wherein the threshold margin is a difference magnitude between the peak sample data point value and a predetermined threshold setting or margin test level. The difference is then analyzed, for example, by determining whether the difference is positive or negative which indicates whether the peak is above or below the margin test level. If the peak is less than the margin test level, a count is incremented. By performing such an analysis for multiple detected peaks over a range of margin test levels, a count distribution is determined which aids a user in determining the threshold margin of the design and thus how close the read channel circuit is to experiencing threshold type errors.
The present invention also relates to a system and method of characterizing the reliability of a read channel circuit with respect to peak shift type errors. The present invention identifies relevant sample data points which are associated with a detected peak and identifies a peak shift amplitude associated therewith, wherein the peak shift amplitude is a value that relates to an amount of peak shift associated with the detected peak. The peak shift amplitude is then compared to a peak shift test level and a count may be incremented based on the comparison. By performing such an analysis for multiple detected peaks over a range of peak shift test levels, a count distribution is determined which aids a user in determining how close a read channel circuit is to experiencing peak shift type errors.
According to one aspect of the present invention, a method of providing error margin information for threshold errors associated with a digital peak detector is disclosed. The method comprises comparing a plurality of peak sample values associated with a digital peak detector portion of the read channel circuit to a threshold margin test level. The method further comprises incrementing a counter each time the threshold margin test level exceeds one of the plurality of peak sample values, wherein a value associated with the counter relates to an amount of threshold margin associated with the digital peak detector. The method may further comprise altering the threshold margin test level a plurality of times and repeating the steps of comparing the plurality of peak sample values to the various altered threshold margin test levels and incrementing the counter. Such repeating results in a count distribution over the plurality of threshold margin test levels, wherein the count distribution provides an indication of an amount of threshold margin associated with the digital peak detector.
According to another aspect of the present invention, a threshold margin channel quality monitor system is disclosed. The system comprises a digital peak detector system operable to detect peaks associated with a read signal and generate a value associated with a magnitude of the detected peaks. The system further comprises a comparison circuit operable to compare the magnitude of a detected peak from the digital peak detector system with a margin test level value, and output a signal indicative of whether the detected peak magnitude is greater than or less than the margin test level. In addition, the system comprises a counter circuit operable to increment a count associated therewith when the comparison circuit signal indicates that the detected peak level is less than the margin test level, such that the count is indicative of a number of detected peaks having amplitudes less than the margin test level. The system may further comprise a control circuit operable to alter the margin test level one or more times after establishing the count for a predetermined number of sample peaks, thereby generating a count distribution as a function of margin test levels. The count distribution may then be used as an indication of the reliability of a read channel circuit with respect to threshold errors.
According to yet another aspect of the present invention, a method of providing error margin information for peak shift errors associated with a digital peak detector is disclosed. The method comprises identifying relevant peak sample data points associated with each of a plurality of detected peaks and determining a peak shift amplitude associated with each of the detected peaks using the identified relevant peak sample data points. The method further comprises comparing the peak shift amplitudes associated with the detected peak to a peak shift test level and incrementing a counter each time the peak shift amplitudes associated with the detected peaks exceed the peak shift test level. In the above manner a value associated with the counter relates to an amount of peak shift margin associated with the digital peak detector.
According to still another aspect of the present invention, the step of identifying relevant peak sample data points comprises identifying three digital sample data points in which at least two of the data points straddle a peak portion of a detected peak. The peak shift amplitude is then determined by subtracting a value associated with a first of the three data points from a value associated with a third of the three data points. Alternatively, the peak shift amplitude is determined by subtracting a value associated with a second of the three data points from a value associated with a greater value of the first or third of the three data points. In such case, a different analysis proceeds with the comparison, wherein a counter is incremented if the peak shift test margin exceeds the peak shift amplitude.
The above method may further comprise repeating the steps of identifying relevant peak sample data points, determining the peak shift amplitudes, comparing the peak shift amplitudes to the peak shift test level, and incrementing the counter for a plurality of different peak shift test levels. In the above manner a count distribution as a function of peak shift test levels is generated, wherein the count distribution provides an indication of how close a read channel circuit is to experiencing peak shift errors.
According to yet another aspect of the present invention, a peak shift margin channel quality monitor system is disclosed. The system comprises a digital peak detector system operable to detect peaks associated with a read signal and provide a plurality of peak sample data points associated with the detected peaks. The system further comprises a comparison circuit operable to compare a peak shift amplitude, which is a value associated with two of the plurality of peak sample data points of a detected peak from the digital peak detector system which reflects a peak shift associated therewith, with a peak shift test level, and output a signal indicative of whether the detected peak shift is greater or less than the peak shift test level. In addition, the system comprises a counter circuit operable to increment a count associated therewith when the signal indicates that the detected peak shift is greater than the peak shift test level. In this manner, the count is indicative of a number of detected peaks having peak shifts greater than the peak shift test level.
According to still another aspect of the present invention, in the above system the plurality of peak sample data points comprise at least three data points, wherein two of the three data points straddle a detected peak. In such circumstances, the comparison circuit comprises a subtraction circuit operable to calculate a difference between a value associated with a first of the three data points and a value associated with a third of the three data points, wherein the difference represents the peak shift amplitude value of the detected peak. The comparison circuit also comprises a second subtraction circuit operable to subtract the peak shift test level from the difference value associated with the detected peak. Lastly, the comparison circuit comprises a threshold detect circuit operable to generate an indication having a state which is a function of whether a subtraction result of the second subtraction circuit is positive or negative.
Alternatively, in the above system the comparison circuit may comprise a subtraction circuit operable to subtract a value associated with a second data point of the three data points from a value associated with a greater value of the first or third of the three data points to generate a peak shift amplitude associated with the detected peak. In the subsequent comparison using, for example, the subtraction circuit, if the peak shift amplitude is less than the peak shift test level, the counter is incremented.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.